1. Field of the Invention
The present invention relates to a semiconductor apparatus including wiring structure under a bump which reduces, in particular, the probability of occurrence of a crack in a semiconductor chip.
2. Description of the Related Art
In the recent years, a semiconductor apparatus which is used for a high-end computer such as backbone communication apparatus is required to undergo high integration and show high-end performance. Accompanied by the demand, high integration, which mounts a lot of chips in one package and results in increase of package size or the number of pins is progressing.
In a multi-pinned package, the number of pins (number of bumps) increases and, therefore, improvement in the yield factor and reliability in the periphery of an under bump metal (equivalent to pad) to become pins at the time of assembly, that is, bumps and their stands is extremely important. Reliability technology related to the periphery of those bump is described in the following patent documents.
Japanese Patent Laid-Open No. 11-186320 discloses structure of arranging no pad of a lower layer immediately under an uppermost layer pad opening window for preventing cracks in a lower layer of the uppermost layer pad but arranging, only in a frame part on one face side among four faces in the uppermost layer pad region, a pad on the lower layer and a via bringing the pad on the lower layer and a pad on the uppermost layer into connection.
Moreover, Japanese Patent Laid-Open No. 2000-340569 discloses structure of forming a reinforcing insulating layer between a pad and a wiring layer immediately under the pad in an attempt to suppress crack occurrence under the pad likewise Japanese Patent Laid-Open No. 11-186320 described above.
However, stress that is concentrated to an edge of UBM (under bump metal), in particular, and an edge of a UBM via in the lower layer of the pad was not brought into consideration for preventing a conventional crack under a pad from occurring. In addition, the directionality of stress such as tensile stress and compressive stress that is present in the lower layer of the pad was not put into consideration, either.
Therefore, in the case of arranging the via in the frame part of only one face among four faces of the pad region as in Japanese Patent Laid-Open No. 11-186320, selection of that one face occasionally strengthens the stress to the contrary. In addition, Japanese Patent Laid-Open No. 2000-340569 is similar as well. The reinforcing insulating layer, which is just arranged, will strengthen the stress under the pad to the contrary according to where the layer is arranged.
Consequently, a device, which was assembled without consideration on where the stress is concentrated under the pad and on the directionality of stress, will result in a great number of occurrences of defects to give rise to cracks in the interlayer film of an LSI wiring layer immediately under the pad.